In many memory applications, memory transistors and conventional CMOS devices are fabricated on a single semiconductor wafer. Typically, the CMOS devices are fabricated in a first region of the wafer, while the memory transistors are fabricated in a second region of the wafer. On some wafers, the memory transistors are fabricated as part of a fieldless array. A fieldless array is defined as an array that does not use field oxide to isolate the various elements of the array. Because field oxide is not required to isolate the memory transistors in a fieldless array, the memory transistors can be laid out with a relatively high density.
In certain applications, conventional CMOS devices (e.g., transistors) are fabricated in the second region, but do not form part of the fieldless array. That is, the CMOS devices located in the second region are isolated by field oxide. Thus, the second region can include both memory transistors and CMOS devices.
In order to distinguish the above-described transistors, the following nomenclature will be used. As used herein, the term "logic transistor" refers to a transistor fabricated in accordance with conventional CMOS processes, regardless of whether the transistor is fabricated in the first region or the second region of the semiconductor wafer. A CMOS logic transistor is isolated from other elements by field oxide. CMOS logic transistors can further be classified as high voltage CMOS logic transistors and low voltage CMOS logic transistors. High voltage CMOS logic transistors have a thicker gate oxide than low voltage CMOS logic transistors, thereby enabling the high voltage CMOS logic transistors to withstand higher gate voltages. The term "fieldless array transistor" refers to a transistor that does not require field oxide isolation. For example, floating gate type non-volatile memory transistor are often used to form a fieldless array.
The process steps required to fabricate high and low voltage CMOS logic transistors are not fully compatible with the process steps required to fabricate fieldless array transistors. As a result, relatively complex processes would be required to form the high and low voltage CMOS logic transistors and the fieldless array transistors on the same wafer. It would therefore be desirable to have an efficient process for fabricating high and low voltage CMOS logic transistors and fieldless array transistors on the same wafer.
In addition, it may be difficult to achieve an acceptable yield when fabricating both CMOS logic transistors and fieldless array transistors on the same wafer. For example, it is anticipated that methods for fabricating the gate electrodes of the fieldless array transistors may result in electrical short circuits between the source and drain regions of the fieldless array transistors. These short circuits may exist for the following reason. During the formation of the CMOS logic transistors, an etch is performed to create the sidewall spacers of the CMOS logic transistors. This etch can expose the silicon between the source and drain regions of the fieldless array transistors. To reduce the resistance of the gate structures of the transistors, a refractory metal is subsequently deposited over the upper surface of the wafer to form self aligned silicide or "salicide" gate electrodes. A silicide layer is formed by reacting this refractory metal with exposed silicon. Thus, a silicide layer forms between the source and drain regions of the fieldless array transistors thereby causing a short circuit. It would therefore be desirable to have a method for fabricating CMOS logic transistors having self aligned silicide gate structures and fieldless array transistors on the same wafer.